integrated circuit systems, inc. general description features ics9159-06 frequency generator and buffer for pentium ? systems 9159-06 rev c 091897 block diagram the i cs9159-06 is a low cost frequency generator designed specifically for pentium systems. the integrated buffer minimizes skew and provides the early cpu clock required by some chipsets such as the opti viper. a 14.318 mhz xtal oscillator provides the reference clock to generate standard pentium frequencies. the cpu clock makes gradual frequency transitions without violating the pll timing of internal microprocessor clock multipliers. asynchronous 33.3 mhz pci bus operation is supported, in-dependent of the cpu operating frequency. green pc systems are supported through power-down, doze, and glitch-free stop clock modes. ? four cpu clocks operate up to 66 mhz at 3.3v with glitch-free start and stop plus smooth transitions ? 3-6ns early cpu clock supports opti viper systems ? selection of 8 frequencies, tristate, or power-down ? six bus clocks support asynchronous pci bus operation ? 250ps skew between synchronous outputs ? integrated buffer outputs drive up to 30pf loads ? 3.1v -5.5v supply range ? 28-pin 300-mil soic package compaq is a trademark of compaq computers. pentium is a trademark of intel corporation. applications ? ideal for green pentium and 486 pci systems functionality 3.1 to 5.5v, 0-70 crystal=14.318 mhz input stp0# stp1# doze# fs(0:1) cpu(0:1) (mhz) cpu2, ecpu bus(0:5) (mhz) ref(0:3) (mhz) 1 x 1 0 0 66.6* 66.6* 33.3 14.318 1 x 1 0 1 60* 60* 33.3 14.318 1 x 1 1 0 50 50 33.3 14.318 1 x 1 11 4 0 40 33.3 14.318 1 x 0 0 0 33.3 33.3 16.7 14.318 1 x 0 0 1 30 30 16.7 14.318 1 x 0 1 0 25 25 16.7 14.318 1 x 0 11 22.5 22.5 16.7 14.318 0 1 1 - - stop run run 14.318 0 0 1 x x stop stop stop 14.318 0 0 * 0 * x x low low low 14.318 0 1 0 x x tristate tristate tristate 14.318 * 3.3 volt operation only. ** 000 mode powers-down the pll sections and forces the outputs low. to ensure glitch- free start and stop of the cpu and bus clocks enter 000 from 001 and exit 000 through 001. product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. preliminary product preview
2 ics9159-06 preliminary product preview pin descriptions 28-pin 300-mil soic pin configuration pin number pin name type description 8, 26 vdd pwr power for logic, cpu and fixed frequency output buffers. 1x1 in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 0.5 - 20 mhz xtal.** 2 x2 out xtal output which includes xtal load capacitance.** 3, 11, 23 gnd pwr ground for logic, cpu and fixed frequency output buffers. 6, 7, 9 cpu(0:2) out processor clock outputs which are a multiple of the input reference frequency as shown in the table. 4, 5 fs(0:1) in frequency multiplier select pins. see table. these inputs have internal pull-up devices. 20 vddb pwr power for bus output buffers. 15, 16, 18 19, 21, 22 bus(0:5) out bus clock outputs are fixed at 33.3 or 16.7 mhz.* 24, 25, 27, 28 ref(0:3) out ref is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 mhz.* 10 ecpu out early processor clock output which is the same frequency as cpu(0:2). this clock leads cpu(0:2) by 3-6ns. 12 doze# in reduces cpu, ecpu and bus clock outputs as shown in the functionality table when at a logic low level. 13, 14 stp0#, stp1# in synchronously stops the cpu, ecpu and bus clocks per the description in the functionality table. can also be used to tristate all outputs when the doze pin is low. 17 gndb pwr this ground return path is brought on separately to permit separating the noise impulses from high output buffers from affecting sensitive internal circuitry.*** * assuming 14.31818 mhz input clock or crystal. * * device provides 18pf load for crystal load capacitance at each pin. *** ground for bus clock buffers.
3 ics9159-06 preliminary product preview absolute maximum ratings electrical characteristics at 3.3v supply v oltage .......................................................................................................... 7.0 v logic inputs ....................................................................... gnd ?0.5 v to v dd +0.5 v ambient operating t emperature ............................................................. 0c to +70c storage t emperature ........................................................................... ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il - - 0.2v dd v input high voltage v ih 0.7v dd --v input low current i il v in =0v -28.0 -10.5 - a input high current i ih v in =v dd -5.0 - 5.0 a output low current 1 i ol v ol =0.8v; for cpu & bus 30.0 47.0 - ma output high current 1 i oh v ol =2.0v; for cpu & bus - -66.0 -42.0 ma output low current 1 i ol v ol =0.8v; for ref 25.0 38.0 - ma output high current 1 i oh v ol =2.0v; for ref - -47.0 -30.0 ma output low voltage v ol i ol =15ma; for cpu & bus - 0.30 .4 v output high voltage 1 v oh i oh =-30ma; for cpu & bus 2.4 2.8 - v output low voltage v ol i ol =12.5ma; for ref - 0.30 .4 v output high voltage 1 v oh i oh =-20ma; for ref 2.4 2.8 - v supply current i dd @66.66 mhz; all outputs unloaded - 55 110 ma supply current, power-down i dd (pd) @000 mode (power-down) - 8 20 ma supply current, stop mode i dd (stop) @001 mode (stop mode) - 35 70 ma
4 ics9159-06 preliminary product preview electrical characteristics at 3.3v v dd = 3.1 ? 3.7 v, t a = 0 ? 70 c note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v, cpu & bus - 0.9 1.5 ns fall time 1 t f1 20pf load, 2.0 to 0.8v, cpu & bus - 0.8 1.4 ns rise time 1 t r2 20pf load, 20% to 80%, cpu & bus - 1.5 2.5 ns fall time 1 t f2 20pf load, 80% to 20%, cpu & bus - 1.4 2.4 ns duty cycle 1 d t 20pf load; @vout=1.4v 40 50 60 % jitter, one sigma 1 t j1s cpu; ecpu load=20pf; fout >25 mhz -60150ps jitter, absolute 1 t jab cpu; ecpu load=20pf, fout >25 mhz -350 - 350 ps jitter, one sigma 1 t j1s bus(0:2); ref(0:3); cpu 3 25 mhz; load=20pf; comp. to the period -0.72.0% jitter, absolute 1 t jab bus(0:2); ref(0:3); cpu 3 25 mhz; load=20pf; comp. to the period -3.0 - 3.0 % input frequency 1 f i 0.5 14.318 20 mhz logic input capacitance 1 cin logic input pins -5-pf crystal oscillator capacitance 1 cinx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1 st crossing of 66.6 mhz v dd supply ramp < 40ms -2.54.5ms frequency settling time 1 t s from 1 st crossing of acquisition to <1% settling -2.04.0ms clock skew window 1 t sk1 cpu to cpu; load=20pf; @1.4v -150250ps clock skew window 1 t sk2 bus to bus and ref to ref; load=20pf; @1.4v -300500ps clock skew window 1 t sk3 ecpu to cpu(0:2); load=20pf; @1.4v 3.0 5.0 6.0 ns
5 ics9159-06 preliminary product preview electrical characteristics at 5.5v v dd = 4.5 ? 5.5 v, t a = 0 ? 70 c note 1: parameter is guaranteed by design and characterization. not 100% tested in production. dc characteristics parameter symbol test conditions min typ max units input low voltage v il --0.2v dd v input high voltage v ih 0.7v dd --v input low current i il v in = 0v -40.0 16.0 - a input high current i ih v in = v dd -5.0 - 5.0 a output low current 1 i ol v ol = 0.8v; for cpu & bus 40.0 62.0 - ma output high current 1 i oh v ol = 2.0v; for cpu & bus - -140.0 -90.0 ma output low current 1 i ol v ol = 0.8v; for ref 30.0 50.0 - ma output high current 1 i oh v ol = 2.0v; for ref - -100.0 -60.0 ma output low voltage v ol i ol = 20ma; for cpu & bus - 0.3 0.4 v output high voltage 1 v oh i oh = -70ma; for cpu & bus 2.4 2.8 - v output low voltage v ol i ol = 15ma; for ref - 0.30 .4 v output high voltage 1 v oh i oh =-50ma; for ref 2.4 2.8 - v supply current i dd @50.0 mhz; all outputs unloaded - 95.0 200.0 ma supply current, power-down i dd (pd) @000 mode (power-down) - 16.0 40.0 ma supply current, stop mode i dd (stop) @001 mode (stop mode) - 70.0 140.0 ma
6 ics9159-06 preliminary product preview electrical characteristics at 5.5v v dd = 4.5 ? 5.5 v, t a = 0 ? 70 c note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v, cpu & bus - 0.55 0.95 ns fall time 1 t f1 20pf load, 2.0 to 0.8v, cpu & bus - 0.52 0.90 ns rise time 1 t r2 20pf load, 20% to 80%, cpu & bus - 1.2 2.1 ns fall time 1 t f2 20pf load, 80% to 20%, cpu & bus - 1.1 2.0 ns duty cycle 1 d t1 20pf load; @vout=1.4v 50 56 70 % duty cycle 1 d t2 20pf load; @vout=50% 40 50 60 % jitter, one sigma 1 t j1s cpu; ecpu load=20pf; fout > 25 mhz - 60 150 ps jitter, absolute 1 t jab cpu; ecpu load=20pf, fout > 25 mhz -350 - 350 ps jitter, one sigma 1 t j1s bus(0:2); ref(0:3); cpu 3 25 mhz; load=20pf; comp. to the period -0.72.0% jitter, absolute 1 t jab bus(0:2); ref(0:3); cpu 3 25 mhz; load=20pf; comp. to the period -3.0 - 3.0 % input frequency 1 f i 0.5 14.318 20 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator capacitance 1 c inx x1, x2 pins - 8 - pf power-on time 1 t on from vdd=1.6v to 1st crossing of 50.0 mhz v dd supply ramp < 40ms -2.54.5ms frequency settling time 1 t s from 1 st crossing of acquisition to < 1% settling -2.04.0ms clock skew window 1 t sk1 cpu to cpu; load=20pf; @1.4v - 150 250 ps clock skew window 1 t sk2 bus to bus and ref to ref; load=20pf; @1.4v - 300 500 ps clock skew window 1 t sk3 ecpu to cpu(0:2); load=20pf; @1.4v 3.0 5.0 6.0 ns
7 ics9159-06 preliminary product preview soic package lead count 28l dimensionl 0.704 ics xxxx m-ppp example: package type m=soic, sop device t ype (consists of 3 or 4 digit numbers) ics=standard device prefix ordering information ICS9159M-06 pattern number(2 or 3 digit number for parts with rom code patterns) product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice.
|
